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VIA EPIA MII Mainboard VIA EPIA MII Mainboard: We take look at VIA's latest Mini-ITX board which features some unique technology.
Date: June 27, 2004
Written By:

Gone are the days when bigger necessarily meant better. More and more as I look around I see a trend to move to smaller things. Smaller cars, smaller portable devices and especially smaller computers are becoming the norm. With space becoming extremely hard to come by, smaller components are necessary to survive. Via has answered the call for small components with the EPIA line of products. Boasting fully featured motherboards in the super small space of 17cm x 17cm is no easy task.

The EPIA MII features some new technology that is fairly innovative. One such feature is built right into the VIA C3 processor, the Via Padlock Advanced Cryptography Engine (ACE). Via Padlock is an encryption and decryption engine designed to be used with the US Government approved Advanced Encryption Standard. Also included onboard are CF and PCMCIA slots which add in one of the major downfalls of these boards, expandability. There are too many features to list here, so here is a list of the specifications.


" VIA C3™/ VIA Eden™ ESP processor

" VIA CLE266 North Bridge, VIA VT8235 South Bridge

System Memory
" 1 DDR266 DIMM socket, Up to 1GB memory size

" Integrated VIA Unichrome™ 2D/3D graphics with MPEG-2 Accelerator, motion compensation and duo-view support

Onboard CardBus / CompactFlash
" CardBus Type I & Type II, Ricoh R5C476 II / R5C485 CardBus Controller

Back Panel I/O
" 1 CardBus Type I and Type II slot, 1 CompactFlash slot
" 1 RJ-45 LAN port
" 1 PS2 mouse port, 1 PS2 keyboard port, 1 Serial port
" 2 USB 2.0 ports
" 1 VGA port, 1 RCA port (SPDIF or TV-Out), 1 S-Video port
" 1 1394 port
" 3 Audio jacks: line-out, line-in and mic-in

Onboard I/O Connectors
" 1 USB connector for 2 additional USB 2.0 ports
" Front-panel audio connectors (mic-in and line-out)
" CD Audio-in connector
" 1 Buzzer
" FIR connector, CIR connector (Switchable for KB/MS)
" Wake-on-LAN
" 1 LPT port header
" CPU/Sys FAN/Fan 3
" 1 Connector for LVDS module (Optional)
" 1 Serial port connector for second COM port

Expansion Slots
" 1 PCI

Onboard IDE
" 2 X UltraDMA 133/100/66 Connector

Onboard Floppy
" 1 x FDD Connector

Onboard LAN
" VIA Networking Tahoe™ VT6103 Fast Ethernet 10/100 PHY-ceiver

Onboard Audio
" VIA Vinyl Six-TRAC Audio AC' 97 codec

Onboard IEEE 1394
" VIA VT6307S IEEE 1394 (Optional)

Onboard TV-Out
" VIA VT1622A TV Out

" Award BIOS, 2/4Mbit flash memory

System Monitoring & Management
" CPU voltage monitoring, Wake-on-LAN, Keyboard Power-on, Timer Power-on, System power management, AC power failure recovery

Form Factor
" Mini-ITX (6 layer)
" 17 cm x 17 cm


Seeing as the EPIA MII has some security features built into the processor I figure a little info on exactly what Via PadLock is would be helpful. Via included an information package which explains the technology extremely well, so here are a couple of sections from it.

The VIA PadLock Hardware Security Suite

The VIA PadLock Hardware Security Suite comprises groundbreaking features that provide a platform approach to computer security, ensuring uncompromising security performance working in concert with leading edge security software. Based on hardware operation, the VIA PadLock Hardware Security Suite consists of two VIA PadLock Random Number Generators (RNGs) and the VIA PadLock Advanced Cryptography Engine (ACE) for US government approved AES encryption and decryption.

The diagram below shows how the VIA PadLock Hardware Security Suite is physically part of the processor die, enabling hardware based RNG and AES cryptographic operation that require minimal processor utilization.

The VIA PadLock RNG

To address this need for good random numbers in security applications, VIA developed the VIA Padlock RNG, integrating a high-performance hardware-based random number generator onto the processor die. This RNG uses random electrical noise on the processor chip to generate highly random values at an extremely fast rate. It provides these numbers directly to security applications via a new x86 instruction that has built-in multitasking support.

Capable of creating random numbers at rates of between 800K to 1600K bits per second, the VIA PadLock RNG addresses the needs of security applications requiring high bit rates that algorithmically increases the quality (randomness) of the entropy produced, for example by applying hashing algorithms to the output.

The VIA PadLock RNG uses a system of Asynchronous Multi-byte Generation, where the hardware generates random bits at its own pace. These accumulate into hardware buffers with no impact on program execution. Software may then read the accumulated bits at any time. This asynchronous approach allows the hardware to generate large amounts of random numbers completely overlapped with program execution. This is opposed to good software generators, which can be fast but consume a significant number of CPU cycles, thereby affecting overall system performance. For more on the VIA PadLock RNG, please visit the web page.

The VIA PadLock RNG has undergone comprehensive testing by leading data security firm, Cryptography Research, Inc.; results show high-performance, high-quality entropy and ease of use. See the complete Cryptography Research report, dated February 27, 2003. For more on the VIA PadLock RNG, visit the website.

AES Encryption

Short for Advanced Encryption Standard, AES is a data encryption technique developed by Belgian cryptographers Joan Daemen and Vincent Rijmen. AES has been adopted by the US Government to replace the current DES encryption standard. The cryptography scheme encrypts and decrypts 128-bit blocks of data with 3 standard key lengths.

1) 128-bit key length that corresponds to approx. 3.4 x 1038 keys

2) 192-bit key length corresponding to approx 6.2 x 1057 keys

3) 256-bit key length corresponding to approx. 1.1 x 1077 keys

In laymen's terms, this means that for each 128-bit key length there can be 3.4 x 1038 possible combinations of "keys". By comparison, the Enigma code used by the Germans in WWII had approx. 1.1 x 107 keys and DES has approx. 7.2 x 1016 keys. To try and put this into perspective, if we assumed a super-computer could break the DES code in one second, it would take the same super computer 149 thousand billion years to decode an AES key with a 128-bit key length.

AES encryption is also particularly well suited for electronic devices such as PCs, IP and mobile phones, PDAs, firewalls, and wireless standards, such as the high-speed 802.11g standard.

The VIA PadLock Advanced Cryptography Engine (ACE)

VIA C5P Nehemiah core processors integrate a powerful Advanced Cryptography Engine (ACE) that can encrypt or decrypt data at a sustained rate of 12.8 GB/s. For a single encryption or decryption, the effective rate can be even faster, up to 21 GB/s. This is faster than any known commercial AES hardware implementation, and several times faster than software implementations carried out with the latest high performance processors.

VIA PadLock ACE directly supports all three AES key sizes (128-bits, 196-bits, and 256-bits) in hardware, and with the same performance. In addition to a single application being able to use VIA PadLock ACE, any number of tasks can use it concurrently without requiring supplemental task management by the application or the operating system. Although implementation of VIA PadLock ACE contains an additional x86 state, the using tasks do not need to save and restore this state - the hardware manages the additional state in a transparent fashion. “

So in laymen's terms, the VIA C3 processor includes an advanced random number generator on-chip, which includes an encryption/decryption engine. Putting the Padlock ACE on-chip removes the software aspect of encryption, making encryption a lot faster. We will see later how the PadLock ACE does using VIA's encryption benchmark.


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